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s6bp401a power management ic for automotive adas platform cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134 - 1709 ? 408 - 943 - 2600 document number: 002 - 03341 rev.*c revised august 9, 2016 quad buck 2.1 mhz dc/dc converter and dual ldo with watchdog timer s6bp401a is a power management ic, consists of quad buck 2.1 mhz dc/dc converter with built - in switching fets, dual low drop - out regulator (ldos) and a digital windowed watchdog timer. having the switching fets built - in, s6bp401a realizes high power conversion efficiency and high switching frequency up to 2.4 mhz . the internal fets are capable to handle up to 3a load. a s s6bp401a employs the current mode architecture, it has fast load transient response. built - in output voltage setting resistors and compensation circuits reduce bom cost and component area. features ? quad buck dc/dc converter (dd1 to dd4) ? vin input range: 4.5v to 5.5v ? switching frequency ? external clock mode: 1.8 mhz to 2.4 mhz ? internal clock mode: 2.0 mhz to 2.2 mhz ? built - in switching fets up to 3a ? built - in output voltage setting resistors ? built - in compensation circuits ? dual ldo (ld1, ld2) ? vin input voltage range: 2.97v to 5.5v ? built - in output voltage setting resistors ? power good monitor output for each dc/dc converters, ldos ? built - in windowed watchdog timer (wdt) ? under voltage lockout (uvlo) ? thermal shutdown (tsd) ? over current protection (ocp) ? over voltage protection (ovp) ? independent enabling for each dc/dc converters and ldos ? load - independent soft - start ? built - in discharge resistors ? small 6 mm 6 mm qfn - 40 package ? aec - q100 compliant (grade - 1) applications ? automotive applications ? advanced driver assistance systems (adas) ? camera systems such as security camera ? industrial applications block diagram 5 1.20v~1.575v / 2a 1.00v~1.275v / 3a 1.20v~2.575v / 2a 3.3v~3.4v / 1a 3.3v~3.4v / 0.2a 1.20v~2.875v / 0.5a s6bp401a : pmic 5v dc/dc converter ldo power good watch dog
document number: 002 - 03341 rev.*c page 2 of 38 s6bp401a more information cypress provides a wealth of data at www.cypress.com/pmic to help you to select the right pmic device for your design, and to help you to quickly and effectively integrate the device into your design. following is an abbreviated list for s6bp401a : ? overview: automotive pmic portfolio , automotive pmic roadmap ? product selector : ? s6bp401a : 6ch automotive pmic for adas ? application notes: cypress offers s6bp401a application notes. recommended application notes for getting started with s6bp401a are: ? an98649 : how to design a power management syste m ? an201006 : thermal considerations and parameters ? evaluation kit operation manual : ? s6sbp401am2sa1001 : p ower block for automotive adas platform ? related products : ? s6bp201a , s6bp202a, s6bp20 3 a : 1ch buck - boost automotive pmic ? s6bp501a , s6bp502a : 3ch automotive pmic for instrument cluster contents features ................................ ................................ ................................ ................................ ................................ ................... 1 applications ................................ ................................ ................................ ................................ ................................ ............ 1 block diagram ................................ ................................ ................................ ................................ ................................ ......... 1 more information ................................ ................................ ................................ ................................ ................................ .... 2 1. typical application ................................ ................................ ................................ ................................ ........................ 3 2. pin configuration ................................ ................................ ................................ ................................ ........................... 4 3. pin functions ................................ ................................ ................................ ................................ ................................ . 5 4. preset output voltage ................................ ................................ ................................ ................................ .................... 6 5. a rchitecture block diagram ................................ ................................ ................................ ................................ .......... 8 6. absolute maximum ratings ................................ ................................ ................................ ................................ ........ 10 7. recommended operating conditions ................................ ................................ ................................ ........................ 11 8. electrical characteristics ................................ ................................ ................................ ................................ ............ 12 9. operating mode list ................................ ................................ ................................ ................................ ..................... 17 10. function ................................ ................................ ................................ ................................ ................................ ........ 18 10.1 turning on and off sequence ................................ ................................ ................................ ................................ .. 18 10.2 over current protection ................................ ................................ ................................ ................................ ............... 20 10.3 over voltage protection ................................ ................................ ................................ ................................ .............. 20 10.4 thermal shutdown (tsd) ................................ ................................ ................................ ................................ ............ 21 10.5 under voltage lockout (uvlo) ................................ ................................ ................................ ................................ ... 21 10.6 soft - start operation ................................ ................................ ................................ ................................ ..................... 21 10.7 discharge operation ................................ ................................ ................................ ................................ .................... 22 10.8 power good monitor and reset function ................................ ................................ ................................ .................... 23 10.9 watchdog timer ................................ ................................ ................................ ................................ .......................... 25 10.10 internal linear regulator output (vreg) ................................ ................................ ................................ .................... 28 11. application circuit example ................................ ................................ ................................ ................................ ........ 29 12. reference data ................................ ................................ ................................ ................................ ............................. 31 13. ordering information ................................ ................................ ................................ ................................ ................... 34 14. package dimens ions ................................ ................................ ................................ ................................ ................... 35 15. major changes ................................ ................................ ................................ ................................ ............................. 36 document h istory ................................ ................................ ................................ ................................ ................................ . 36 sales, solutions, and legal information ................................ ................................ ................................ ............................. 38
document number: 002 - 03341 rev.*c page 3 of 38 s6bp401a 1. typical application figure 1 - 1 typical application
document number: 002 - 03341 rev.*c page 4 of 38 s6bp401a 2. pin configuration figure 2 - 1 pin configuration pgl2 gnd ldo2 pvccl2 pvccl1 ldo1 vcc pg1 vreg pg2 pg4 fb1 fb4 pvcc1 pvcc4 lx1 lx4 pgnd1 pgnd4 pgnd2 pgnd3 pgnd2 lx3 lx2 pvcc3 lx2 fb3 pvcc2 pg3 pvcc2 sync wdi rst enl2 enl1 en4 en3 en2 en1 fb2 (corner pad) (corner pad) (corner pad) (corner pad) cp1 cp4 cp3 cp2 17 18 19 20 11 12 13 14 15 16 8 23 9 22 10 21 1 7 24 2 top view 29 3 28 4 27 5 26 ep (exposed pad) 6 25 30 40 39 38 37 36 35 34 33 32 31
document number: 002 - 03341 rev.*c page 5 of 38 s6bp401a 3. pin functions table 3 - 1 pin functions f unctional b lock pin number pin name i/o description pin setting w hen not b eing used dd1 19 en1 i enable input terminal of dd1 . ground 30 fb 1 i output voltage feedback terminal of dd1 . ground 33 pg1 o power good output terminal of dd1. ground 29 pvcc1 - power supply terminal of dd1 . vcc 28 lx1 o inductor connect terminal of dd1 . leave pin open 27 pgnd1 - power ground terminal of dd1 . ground dd2 18 en2 i enable input terminal of dd 2. ground 20 fb 2 i output voltage feedback terminal of dd 2. ground 31 pg2 o power good output terminal of dd2. ground 21, 22 pvcc2 - power supply terminal of dd 2. vcc 23, 24 lx2 o inductor connect terminal of dd 2. leave pin open 25, 26 pgnd2 - power ground terminal of dd 2. ground dd3 17 en3 i enable input terminal of dd 3. ground 9 fb 3 i output voltage feedback terminal of dd 3. ground 10 pg3 o power good output terminal of dd3. ground 8 pvcc3 - power supply terminal of dd 3. vcc 7 lx3 o inductor connect terminal of dd 3. leave pin open 6 pgnd3 - power ground terminal of dd 3. ground dd4 16 en4 i enable input terminal of dd 4. ground 2 fb 4 i output voltage feedback terminal of dd 4. ground 1 pg4 o power good output terminal of dd4. ground 3 pvcc4 - power supply terminal of dd 4. vcc 4 lx4 o inductor connect terminal of dd 4. leave pin open 5 pgnd4 - power ground terminal of dd 4. ground ld1 15 enl1 i enable input terminal of ld1 . ground 36 pvccl1 - power supply terminal of ld1 . vcc 35 ldo1 o output terminal of ld1 . leave pin open ld2 14 enl2 i enable input of ld2 . ground 40 pgl2 o power good output terminal of ld2. ground 37 pvccl2 - power supply terminal of ld2 . vcc 38 ldo2 o output terminal of ld2 . leave pin open wdt 12 wd i i trigger input terminal of wdt. ground 13 rst o reset input terminal of wdt. ground sync 11 sync i external clock input terminal. ground - 34 vcc - power supply terminal for analog controller. ? - 32 v reg o internal 1.8v supply voltage capacitor terminal. do not supply or load this terminal externally. ? - 39 gnd - ground terminal for analog controller. ? - ep ep - exposed pad. connect to ground plane. ? - cp1, cp2, cp3, cp4 cp - corner pad for reinforcing attachment to a board. connect to ground plane. ?
document number: 002 - 03341 rev.*c page 6 of 38 s6bp401a 4. preset output voltage table 4 - 1 preset output voltage (buck dc/dc converter) channel preset o utput v oltage [v] soft - start t ime [ms] maximum o utput c urrent [ma] under v oltage t hreshold [%] over v oltage t hreshold [%] dd1 1.2 0 0 1.2 0 0 2000 94.0 106.0 1.2 25 1.2 2 5 1.250 1.250 1.275 1.275 1.300 1.300 1.325 1.325 1.500 1.500 1.525 1.525 1.550 1.550 1.575 1.575 dd2 1.000 1.000 3000 94.0 106.0 1.025 1.025 1.050 1.050 1.075 1.075 1.100 1.100 1.125 1.125 1.150 1.150 1.175 1.175 1.200 1.200 1.225 1.225 1.250 1.250 1.275 1.275 dd3 1.200 1.200 2000 95.2 106.0 1.225 1.225 1.250 1.250 1.275 1.275 1.500 1.500 1.525 1.525 1.550 1.550 1.575 1.575 1.800 1.800 1.825 1.825 1.850 1.850 1.875 1.875 2.500 2.500 2.525 2.525 2.550 2.550 2.575 2.575 dd4 3.300 3.300 1000 95.5 106.0 3.325 3.325 3.350 3.350 3.375 3.375 3.400 3.400 note s : ? soft - start time values are at f osc = 2.1 mhz ? refer to chapter 8 for the minimum or maximum values of output voltage , under voltage threshold and over voltage threshold .
document number: 002 - 03341 rev.*c page 7 of 38 s6bp401a table 4 - 2 preset output voltage (ldo) channel preset o utput v oltage [v] soft - start t ime [ms] maximum o utput c urrent [ma] under v oltage t hreshold [%] over v oltage t hreshold [%] ld1 3.300 3.300 200 94.0 106.0 3.325 3.325 3.350 3.350 3.375 3.375 3.400 3.400 ld2 1.200 1.200 500 94.0 106.0 1.225 1.225 1.250 1.250 1.275 1.275 1.800 1.800 1.825 1.825 1.850 1.850 1.875 1.875 2.800 2.800 2.825 2.825 2.850 2.850 2.875 2.875 n ote s : ? soft - start time values are at f osc = 2.1 mhz ? refer to chapter 8 for the minimum or maximum values of output voltage , under voltage threshold and over voltage threshold .
document number: 002 - 03341 rev.*c page 8 of 38 s6bp401a 5. architecture block diagram figure 5 - 1 architechture block diagram error amplifier slope compensation pwm logic control pwm comparator current sense anti - shoot through low priority en1 voltage reference power good monitor peak current comparator fb1 pvcc1 lx1 pgnd1 << dd1 >> pgnd2 pvcc2 lx2 discharge ss1 clk pg1 error amplifier slope compensation pwm logic control pwm comparator current sense anti - shoot through low priority en2 voltage reference power good monitor peak current comparator fb2 pvcc2 lx2 pgnd2 << dd2 >> discharge ss2 clk pg2 error amplifier slope compensation pwm logic control pwm comparator current sense anti - shoot through low priority en3 voltage reference power good monitor peak current comparator fb3 pvcc3 lx3 pgnd3 << dd3 >> discharge ss3 clk pg3 error amplifier slope compensation pwm logic control pwm comparator current sense anti - shoot through low priority en4 voltage reference power good monitor peak current comparator fb4 pvcc4 lx4 pgnd4 << dd4 >> discharge ss4 clk pg4
document number: 002 - 03341 rev.*c page 9 of 38 s6bp401a en1 en2 en3 en4 enl1 enl2 sync vcc vreg gnd pg1 pg2 pg3 pg4 rst control logic pg1 pg2 pg3 pg4 watchdog timer pgl1 oscillator with synchronization clk thermal shutdown under voltage lockout clk en1 en2 en3 en4 enl1 enl2 soft - start control ss1 ss2 ss3 ss4 ssl1 enl2 linear regulator vcc vcc << main control >> << power good monitor output >> << watchdog timer >> wdi clk power good monitor pvccl1 low priority voltage reference power good monitor ldo1 << ldo1 >> discharge enl1 ssl1 pgl1 pvccl2 low priority voltage reference power good monitor ldo2 << ldo2 >> discharge enl2 ssl2 pgl2 pgl2 pgl2
document number: 002 - 03341 rev.*c page 10 of 38 s6bp401a 6. absolute maximum ratings table 6 - 1 absolute maximum ratings parameter symbol condition rating unit min max power supply voltage v vcc vcc - 0.3 + 6.9 v v pvcc pvcc1, pvcc2, pvcc3, pvcc4 - 0.3 + 6.9 v v pvccl pvccl1, pvccl2 - 0.3 + 6.9 v input voltage v en en1, en2, en3, en4, en l 1 , en l 2 - 0.3 + 6.9 v v wdi wd i - 0.3 + 6.9 v v sync sync - 0.3 + 6.9 v v fb fb 1, fb 2, fb 3, fb 4 - 0.3 + 6.9 v v pg pg1, pg2, pg3, pg4, pgl2 - 0.3 + 6.9 v v rst rst - 0.3 + 6.9 v lx voltage v lx lx1, lx2, lx3, lx4 - 0.3 + 6.9 v voltage difference v pvcc - vcc pvcc1 - vcc, pvcc2 - vcc, pvcc3 - vcc, pvcc4 - vcc - 0.3 + 0.3 v v pgnd - gnd pgnd1 - gnd, pgnd2 - gnd, pgnd3 - gnd, pgnd4 - gnd - 0.3 + 0.3 v v pvcc - lx pvcc1 - lx1, pvcc2 - lx2, pvcc3 - lx3, pvcc4 - lx4 - 0.3 + 6.9 v v vcc - input vcc - en1, vcc - en2, vcc - en3, vcc - en4, vcc - en1l, vcc - en2l, vcc - wdi, vcc - sync, vcc - fb1, vcc - fb2, vcc - fb3, vcc - fb4 - 0.3 + 6.9 v power dissipation p d t a + 25 c, thermal resistance ( ja ) : 18 c /w (*1) - 6940 mw junction temperature t j - - 40 + 150 c storage temperature t stg - - 55 + 150 c *1: when the ic is mounted on 7 6.2 mm 114.3 mm four - layer epoxy board. ic is mounted on a four - layer epoxy board, which terminal bias, and the ics thermal pad is connected to the epoxy board. warning 1. semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or temperature) in excess of absolute m aximum ratings. do not exceed any of these ratings. figure 6 - 1 maximum power di ssipation - operating a mbient t emperature characteristics 0 1000 2000 3000 4000 5000 6000 7000 8000 -60 -40 -20 0 20 40 60 80 100 120 140 maximum power dissipation p d [mw] ambient temperature t a [ c]
document number: 002 - 03341 rev.*c page 11 of 38 s6bp401a 7. recommended operating conditions table 7 - 1 recommended operating conditions parameter symbol condition value unit min typ max power supply voltage v vcc vcc + 4.5 + 5.0 + 5.5 v v pvcc pvcc1, pvcc2, pvcc3, pvcc4 - v vcc - v v pvccl pvccl1, pvccl2 + 2.97 + 5.0 v vcc v input voltage v en en1, en2, en3, en4, e nl 1 , en l 2 0 - v vcc v v wdi wd i 0 - v vcc v v sync sync 0 - v vcc v v fb fb 1, fb 2, fb 3, fb 4 0 - v vcc v v pg pg1, pg2, pg3, pg4, pgl2 0 - + 5.5 v v rst rst 0 - + 5.5 v operating ambient temperature t a - - 40 + 25 + 125 c warning: 1. the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the device's electrical characteristics are warranted when the device is operated under these conditions. 2. any use of semiconductor devices will be under their recommended operating condition. 3. operation under any conditions other than these conditions may adversely affect reliability of device and could result in dev ice failure. 4. no warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet. if you are considering application under any conditions other than listed herein, please contact sales representatives beforehand.
document number: 002 - 03341 rev.*c page 12 of 38 s6bp401a 8. electrical characteristics v vcc = v pvcc = 5.0v, v pvccl = 5.0v, t a = t j = - 40 to + 125 c, unless otherwise noted. typical values are at t a = +25 c . table 8 - 1 electrical characteristics parameter symbol condition value unit min typ max supply c urrent shutdown current i vccs vcc pin, v en1 = v en2 = v en3 = v en4 = v enl1 = v enl2 = 0v - 1 10 a uvlo: under v oltage l ockout (vcc) threshold voltage v uvlof v vcc falling, uvlo stop voltage 3.80 3.95 4.10 v hysteresis v uvhys - 0.27 0.30 0.33 v tsd: thermal s hutdown shutdown temperature t tsd temperature rising - 165 (*1) - c hysteresis t tsdhys - - 10 (*1) - c enable i nputs (en1, en2, en3, en4, enl1, enl2) input high voltage v ih en - 2.0 - v vcc v input low voltage v il en - 0 - 0.4 v input current i ih en v en = 5.0v 33 50 100 a pull down resistance r pd en - 50 1 00 150 k ? internal l inear r egulator o utput (v reg ) output voltage v v reg v vcc = 5.0v 1.7 4 1.8 0 1. 86 v maximum output current i v reg v vcc = 5.0v 5 - - ma over voltage lockout threshold v vregovr v vreg rising, power fail 1.86 1.92 1.98 v v vregovf v vreg falling, power good 1.81 1.87 1.93 v under voltage lockout threshold v vreguvr v vreg rising, power good 1.67 1.73 1.79 v v vreguvf v vreg falling, power fail 1.62 1.68 1.74 v oscillator switching frequency f osc - 2.0 2.1 2.2 mhz synchronization i nput (sync) input high voltage v ih sync - 2.0 - v vcc v input low voltage v il sync - 0 - 0.4 v input current i ih sync v en = 5.0v 33 50 100 a pull down resistance r pd sync - 50 1 00 150 k ? input frequency f sync - 1.8 2.1 2.4 m hz switching frequency f osc - - f sync - m hz
document number: 002 - 03341 rev.*c page 13 of 38 s6bp401a parameter symbol condition value unit min typ max power good monitor (pg1, pg2, pgl2) over voltage threshold v pgov ratio of power fail threshold to v out1 , v out2 , v outl2 rising 104.5 106.0 107.5 % over voltage hysteresis v pgovhys - 0.5 1.0 1.5 % under voltage threshold v pguv ratio of power fail threshold to v out1 , v out2 , v out3 falling 92.5 94.0 95.5 % under voltage hysteresis v pguvhys - 0.5 1.0 1.5 % l eakage current i leakpg v pg = 5.0v - - 1 a output low voltage v olpg i pg = 3 ma - 0.15 0.30 v propagation time t ppg 5% outside of the threshold, power fail - 4 (*1) 8 (*1) s power - on reset time t rpg power good 8 10 12 ms power good monitor (pg3) over voltage threshold v pgov ratio of power fail threshold to v out3 rising 104.5 106.0 107.5 % over voltage hysteresis v pgovhys - 0.5 1.0 1.5 % under voltage threshold v pguv ratio of power fail threshold to v out3 falling 93.7 95.2 96.7 % under voltage hysteresis v pguvhys - 0.5 1.0 1.5 % l eakage current i leakpg v pg = 5.0v - - 1 a output low voltage v olpg i pg = 3 ma - 0.15 0.30 v propagation time t ppg 5% outside of the threshold, power fail - 4 (*1) 8 (*1) s power - on reset time t rpg power good 8 10 12 ms power good monitor (pg4) over voltage threshold v pgov r atio of power fail threshold to v out4 rising 104.5 106.0 107.5 % over voltage hysteresis v pgovhys - 0.5 1.0 1.5 % under voltage threshold v pguv ratio of power fail threshold to v out4 falling 94.0 95.5 97.0 % under voltage hysteresis v pguvhys - 0.5 1.0 1.5 % l eakage current i leakpg v pg = 5.0v - - 1 a output low voltage v olpg i pg = 3 ma - 0.15 0.30 v propagation time t ppg 5% outside of the threshold, power fail - 4 (*1) 8 (*1) s power - on reset time t rpg power good 8 10 12 ms reset (rst) over voltage threshold v rsov r atio of power fail threshold to v out l1 rising 104.5 106.0 107.5 % over voltage hysteresis v rsovhys - 0.5 1.0 1.5 % under voltage threshold v rsuv ratio of power fail threshold to v out l1 falling 92.5 94.0 95.5 % under voltage hysteresis v rsuvhys - 0.5 1.0 1.5 % l eakage current i leakrst v rst = 5.0v - - 1 a output low voltage v olrst i pg = 3 ma - 0.15 0.30 v propagation time t prst 5% outside of the threshold, power fail - 4 (*1) 8 (*1) s power - on reset time t rd power good 25.6 32.0 38.4 ms
document number: 002 - 03341 rev.*c page 14 of 38 s6bp401a parameter symbol condition value unit min typ max watchdog timer (wdi) watchdog sampling time t sam - 0.40 0.50 0.60 ms ignore window time t iw - 25.6 32.0 38.4 ms open window time t ow - 25.6 32.0 38.4 ms long open window time t low - 102.4 128.0 153.6 ms closed window time t cw - 25.6 32.0 38.4 ms window watchdog trigger time t wd - 38.4 48 51.2 ms input high voltage v ih wdi - 2.0 - v vcc v input low voltage v il wdi - 0 - 0.4 v input current i ih wdi v wdi = 5.0v 33 50 100 a pull down resistance r pd wdi - 50 1 00 150 k ? dd1: buck dc/dc c onverter output voltage accuracy v out1 v vcc = 5.0v, i out1 = 10 ma - 1.8 0 +1.8 % dc regulation v reg1 v vcc = v pvcc1 = 4.5 to 5.5v, i out1 = 0 to 2.0a - 15 (*1) 0 +5 (*1) m v fb1 input resistance r fb1 v fb1 = 2.0v 95 190 285 k ? switching fet on resistance r onhs1 i lx1 = 20 ma (pvcc1 to lx1) - 1 00 190 m ? r onls1 i lx1 = - 20 ma (lx1 to pgnd1) - 65 125 m ? switching fet leakage current i leak1 i pvcc1 = 5.0v - 1 10 a maximum output current i out1 l = 1.5 h 2 (*1) - - a lx1 peak current limit i limit1 l = 1.5 h 2.5 (*1) - - a over voltage protection threshold v ovp1 v out1 rising, switching termination threshold 125.0 130.0 135.0 % over voltage protection hysteresis v ovphys1 - 2.0 5.0 8.0 % fb1 discharge resistance r dis1 - 160 400 640 ? soft - start time coefficient t coess1 t ss1 = v out 1 x t coess1 0.9 1.0 1.1 ms/v dd2: buck dc/dc c onverter output voltage accuracy v out2 v vcc = 5.0v, i out2 = 10 ma - 1.8 0 +1.8 % dc regulation v reg2 v vcc = v pvcc2 = 4.5 to 5.5v i out2 = 0 to 3.0a - 15 (*1) 0 +5 (*1) m v fb2 input resistance r fb2 v fb2 = 2.0v 95 190 285 k ? switching fet on resistance r onhs2 i lx2 = 20 ma (pvcc2 to lx2) - 85 165 m ? r onls2 i lx2 = - 20 ma (lx2 to pgnd2) - 55 105 m ? switching fet leakage current i leak2 i pvcc2 = 5.0v - 1 10 a maximum output current i out2 l = 1.5 h 3 (*1) - - a lx2 peak current limit i limit2 l = 1.5 h 3.5 (*1) - - a over voltage protection threshold v ovp2 v out2 rising, switching termination threshold 125.0 130.0 135.0 % over voltage protection hysteresis v ovphys2 - 2.0 5.0 8.0 % fb2 discharge resistance r dis2 - 160 400 640 ? soft - start time coefficient t coess2 t ss2 = v out2 x t coess2 0.9 1.0 1.1 ms/v
document number: 002 - 03341 rev.*c page 15 of 38 s6bp401a parameter symbol condition value unit min typ max dd3: buck dc/dc c onverter output voltage accuracy v out3 v vcc = 5.0v, i out3 = 10 ma - 1.8 0 +1.8 % dc regulation v reg3 v vcc = v pvcc3 = 4.5 to 5.5v, i out3 = 0 to 2.0a - 15 (*1) 0 +5 (*1) m v fb3 input resistance r fb3 v fb3 = 2.0v 95 190 285 k ? switching fet on resistance r onhs3 i lx3 = 20 ma (pvcc3 to lx3) - 100 190 m ? r onls3 i lx3 = - 20 ma (lx3 to pgnd3) - 65 125 m ? switching fet leakage current i leak3 i pvcc3 = 5.0v - 1 10 a maximum output current i out3 l = 1.5 h 2 (*1) - - a lx3 peak current limit i limit3 l = 1.5 h 2.5 (*1) - - a over voltage protection threshold v ovp3 v out3 rising, switching termination threshold 125.0 130.0 135.0 % over voltage protection hysteresis v ovphys3 - 2.0 5.0 8.0 % fb3 discharge resistance r dis3 - 160 400 640 ? soft - start time coefficient t coess3 t ss3 = v out 3 t coess3 0.9 1.0 1.1 ms/v dd4: buck dc/dc c onverter output voltage accuracy v out4 v vcc = 5.0v, i out4 = 10 ma - 1.8 0 +1.8 % dc regulation v reg4 v vcc = v pvcc4 = 4.5 to 5.5v, i out4 = 0 to 1.0 a - 15 (*1) 0 +5 (*1) m v fb4 input resistance r fb4 v fb4 = 2.0v 95 190 285 k ? switching fet on resistance r onhs4 i lx4 = 20 ma (pvcc4 to lx4) - 100 190 m ? r onls4 i lx4 = - 20 ma (lx4 to pgnd4) - 65 125 m ? switching fet leakage current i leak4 i pvcc4 = 5.0v - 1 10 a maximum output current i out4 l = 1.5 h 1 (*1) - - a lx4 peak current limit i limit 4 l = 1.5 h 1.5 (*1) - - a over voltage protection threshold v ovp4 v out4 rising, switching termination threshold 125.0 130.0 135.0 % over voltage protection hysteresis v ovphys4 - 2.0 5.0 8.0 % fb4 discharge resistance r dis4 - 160 400 640 ? soft - start time coefficient t coess4 t ss4 = v out 4 t coess4 0.9 1.0 1.1 ms/v
document number: 002 - 03341 rev.*c page 16 of 38 s6bp401a parameter symbol condition value unit min typ max ld1: ldo r egulator output v oltage accuracy v outl1 v vcc = 5.0v, i outl1 = 10 ma - 1.8 0 +1.8 % dc regulation v regl1 v vcc = 4.5 to 5.5v, v pvccl1 = 2.97 to v vcc i outl1 = 0 to i outl1 - 15 (*1) 0 +5 (*1) m v output fet l eakage current i leakl1 i pvccl1 =5.0v - 1 10 a maximum o utput current i outl1 v pvccl1 - v out l 1 1. 6v 200 (*1) - - ma 0.17v v pvccl1 - v out l 1 < 1.6v 100 (*1) - - ma output current limit i limitl1 v pvccl1 - v out l 1 1.6v 2 1 0 (*1) - - ma 0.17v v pvccl1 - v out l 1 < 1.6v 1 05 (*1) - - ma ldo1 discharge resistance r disl1 - 160 400 640 ? soft - start time coefficient t coessl1 t ssl 1 = v out l1 t coessl1 0.9 1.0 1.1 ms/v ld2: ldo r egulator output v oltage accuracy v outl2 v vcc = 5.0v , i outl2 = 10 ma - 1.8 0 +1.8 % dc regulation v regl2 v vcc = 4.5 to 5.5v, v pvccl 2 = 2.97 to v vcc i outl2 = 0 to i outl2 - 15 (*1) 0 +5 (*1) mv output fet l eakage current i leakl2 i pvccl2 =5.0v - 1 10 a maximum o utput current i outl2 v pvccl 2 - v out l2 1.6v 500 (*1) - - ma 0.17v v pvccl 2 - v out l2 < 1.6v 400 (*1) - - ma output current limit i limitl2 v pvccl 2 - v out l2 1.6v 5 25 (*1) - - ma 0.17v v pvccl 2 - v out l2 < 1.6v 4 2 0 (*1) - - ma ldo 2 discharge resistance r disl2 - 160 400 640 ? soft - start time coefficient t coessl2 t ssl2 = v out l 2 t coessl2 0.9 1.0 1.1 ms /v * 1: the electrical characteristic is ensured by statistical characterization and indirect tests.
document number: 002 - 03341 rev.*c page 17 of 38 s6bp401a 9. operating mode list table 9 - 1 shows the operation list of s6bp401a. table 9 - 1 operation mode list condition operating b lock t j sync enl1 en1/ en2 / en3 / en4 / enl2 chip control v reg ldo watch - dog trigger monitor freq. sync. ld1 dd1/ dd2 / dd3 / dd4 / ld2 < t tsd l or h l l off off off off off off < t tsd l or h l h on on off off off on < t tsd l or h h l on on on off on off < t tsd l or h h h on on on off on on < t tsd clock l l off off off off off off < t tsd clock l h on on off on off on < t tsd clock h l on on on on on off < t tsd clock h h on on on on on on t tsd l or h l l off off off off off off t tsd l or h l h on on off off off off t tsd l or h h l on on off off off off t tsd l or h h h on on off off off off t tsd clock l l off off off off off off t tsd clock l h on on off off off off t tsd clock h l on on off off off off t tsd clock h h on on off off off off
document number: 002 - 03341 rev.*c page 18 of 38 s6bp401a 10. function 10.1 turning on and off sequence when all of the enable input terminals (en1, en2, en3, en4, enl1 and enl2) are low, the device is in shutdown state. when any one or more than one of them go high, the device is initialized, then the internal linear regulator (vreg) starts gen erating 1.8v internal supply voltage. after that, each dc/dc converters and ldos state is transitioned to the state which can be started. in order for the device to start, the vcc terminal voltage must be higher than the under - voltage lockout threshold ( v u vlof + v uvhys ). figure 10 - 1 depicts the turning - on and off sequence where the enable signals are connected to vcc. figure 10 - 2 depicts that where the enable signals are respectively controlled after the ic is powered. figure 10 - 1 turning on and off sequence (where en1 and enl1 are c onnected to vcc) *1: given that the system employs the same external parts with those specified in 11 . application circuit example . time v rst v vreg v outl1 v out1 v pguv +v pguvhys v enl1 v en1 v vcc v rsuv +v rsuvhys initialization (typ: 1ms) t rd v uvlof typ:40.5ms(*1) 10% 10% typ:0.92ms(*1) v uvlof + v uvhys
document number: 002 - 03341 rev.*c page 19 of 38 s6bp401a figure 10 - 2 turning on and off sequence (where en1 and enl1 are r espectively c ontrolled) *1: given that the system employs the same external parts with those specified in 11 . application circuit example . time v rst v vreg v outl1 v out1 v pguv +v pguvhys v enl1 v en1 v vcc v rsuv +v rsuvhys initialization (typ:1ms) t rd initialization (typ:1ms) 10% 10% typ:40.5ms(*1) typ:0.92ms(*1) v uvlof + v uvhys
document number: 002 - 03341 rev.*c page 20 of 38 s6bp401a 10.2 over current protection the over current protection of the dc/dc converters detects the inductor peak current with on - resistance of internal high side switching fet. if the dc/dc converter is over current sta te, the corresponding output voltage is decreased. if the device returns from over current state, the output voltage is target voltage. each ldos equips foldback current limiter in order to prevent the ic itself from being damaged or destroyed. the curve o f output current and output voltage in over current state is shown in the figure 10 - 3 . figure 10 - 3 ldo foldback over current protection characteristic 10.3 over voltage protection the over voltage protection of the dc/dc converters detects the output voltage. i f the dc/dc converter is over voltage state, the corresponding channel stops switching and i nductor connect ing terminal (lx1, lx2, lx3, lx4) is held at high impedance. i f the device returns from over voltage state, the channel returns switching automatically. figure 10 - 4 over voltage protection timing chart current voltage i outl1 i outl2 i limitl1 i limitl2 v outl1 v outl2 i sl1 i sl2 time v pg1 ,v pg2 , v pg3 ,v pg4 t rpg t ppg v en1 ,v en2 , v en3 ,v en4 v out1 ,v out2 , v out3 ,v out4 t rpg v pgovhys v pgov hi - z on lx1, lx2, lx3, lx4 discharge off switching hi - z switching v ovp1 , v ovp2 , v ovp3 , v ovp4 v ovphys1 , v ovphys2 , v ovphys3 , v ovphys4
document number: 002 - 03341 rev.*c page 21 of 38 s6bp401a 10.4 thermal shutdown (tsd) if the junction temperature reaches +165c, a ll dc/dc converters and ldos stop outputting voltage. then the discharge operation is carried out to discharge the output capacitor (the discharge operation continues until the state of the thermal shutdown r eleased.) when the junction temperature drops be low +155c, the soft - starters activate regulators and start generating voltage gradually if the enable is "high." figure 10 - 5 thermal s hutdown timing chart 10.5 under voltage lockout (uvlo) if the vcc terminal voltage (v vcc ) drops below the lower uvlo threshold (v uvlo f ), all dc/dc converters (dd1, dd2, dd3, dd4), ldos (ld1, ld2), windowed watchdog timer (wdt) and the internal linear regulator (vreg) stop working. when the vcc terminal voltage (v vcc ) is raised higher than the higher uvlo threshold (v uvlo f + v uvhys ), the device returns automatically. 10.6 soft - start operation s6bp401a equips load - independent soft - start function in order to prevent the dc/dc converters and ldos from having rush current at the s tart - up. the soft - start timing is shown in the figure 10 - 6 , and is given by the following equation; ? ?? = ? ??? ? ????? , where t ss [ms] : soft - start time v out [v] : output voltage (v out1 , v out2 , v out3 , v out4 , v outl1 , v outl2 ) t coess [ms/v] : soft - start time coefficient (t coess1 , t coess2 , t coess3 , t coess4 , t coessl1 , t coessl2 ) 165 deg. 155 deg. t j v en1 v out1 time soft - start soft - start
document number: 002 - 03341 rev.*c page 22 of 38 s6bp401a figure 10 - 6 soft - start operation timing chart 10.7 discharge operation when an enable signal goes low, the corresponding output capacitor is discharged by the internal discharge resistor and the output voltage is decreased gradually. note that the discharge time is not consistent: it depends on the output load current. as for a dc/dc converter, the output capacitor is discharged from fb1, fb2, fb3 and fb4 terminal to pgnd1, pgnd2, pgnd3 and pgnd4 terminal respectively. as for a ldo, the output capacitor is dis - charge d from ldo1, ldo2 terminal to gnd terminal. the discharge time required to decrease the output voltage by 90% without any explicit load given by the following equation; ? ??? = 2 . 3 ? ??? ? ??? , where t dis [ms] : discharge time r dis [k ? ] : discharge resistance (r dis1 , r dis2 , r dis3 , r dis4 , r disl1 , r disl2 ) c out [ f] : output capacitor figure 10 - 7 discharge diagram (dc/dc converter) enable error amp. pwm control power supply pvcc1,pvcc2, pvcc3,pvcc4 lx1,lx2, lx3,lx4 pgnd1,pgnd2, pgnd3,pgnd4 fb1,fb2, fb3,fb4 r dis1 , r dis2 , r dis3 , r dis4 v en v out time t ss =v out (1) t coess v out (1) v out (2) v out (3) t ss =v out (2) t coess t ss =v out (3) t coess
document number: 002 - 03341 rev.*c page 23 of 38 s6bp401a figure 10 - 8 discharge diagram (ldo) 10.8 power good monitor and reset function each dc/dc converters and ldos has power good function to indicate whether the output voltage is in the expected range. the table 10 - 1 describes the power good pin names and their functions of each dc/dc converters and ldos. the figure 10 - 9 and figure 10 - 10 depict power - good timing chart. table 10 - 1 power good monitor and reset function pin list c hannel pin name description dd 1 pg 1 enabling dd1 is followed by rising of the dd1 output voltage (v out1 ). once v out1 reaches within the power good range (v pguv + v pguvhys < v out1 < v pgov C v pgovhys ) , the power good monitor output (pg1 terminal) changes its state from low to open after a power - on - reset time (t rpg ). when v out1 is out of the power good range (v out1 v pguv or v out1 v pgov ), pg1 terminal changes its state from open to low after the propagation delay (t ppg ). the glitch within t ppg does not affect the power good monitor output. dd2 pg2 enabling dd2 is followed by rising of the dd2 output voltage (v out2 ). once v out2 reaches within the power good range (v pguv + v pguvhys < v out2 < v pgov C v pgovhys ) , the power good monitor output (pg2 terminal) changes its state from low to open after a power - on - reset time (t rpg ). when v out2 is out of the power good range (v out2 v pguv or v out2 v pgov ), pg2 terminal changes its state from open to low after the propagation delay (t ppg ). the glitch within t ppg does not affect the power good monitor output. dd3 pg3 enabling dd3 is followed by rising of the dd3 output voltage (v out3 ). once v out3 reaches within the power good range (v p guv + v pguvhys < v out3 < v pgov C v pgovhys ) , the power good monitor output (pg3 terminal) changes its state from low to open after a power - on - reset time (t rpg ). when v out3 is out of the power good range (v out3 v pguv or v out3 v pgov ), pg3 terminal changes its state from open to low after the propagation delay (t ppg ). the glitch within t ppg does not affect the power good monitor output. dd4 pg4 enabling dd4 is followed by rising of the dd4 output voltage (v out4 ). once v out4 reaches within the po wer good range (v pguv + v pguvhys < v out4 < v pgov C v pgovhys ) , the power good monitor output (pg4 terminal) changes its state from low to open after a power - on - reset time (t rpg ). when v out4 is out of the power good range (v out4 v pguv or v out4 v pgov ) , pg4 terminal changes its state from open to low after the propagation delay (t ppg ). the glitch within t ppg does not affect the power good monitor output. enable power supply pvccl1,pvccl2 ldo1,ldo2 r disl1 , r disl2
document number: 002 - 03341 rev.*c page 24 of 38 s6bp401a c hannel pin name description ld1 rst enabling ld1 is followed by rising of the ld1 output voltage (v outl1 ). once v outl1 rea ches within the power good range (v rsuv + v rsuvhys < v outl1 < v rsov - v rsovhys ) , the rst terminal changes its state from low to open after a power - on - reset time (t rd ). when v outl1 is out of the power good range (v outl1 v rsuv or v outl1 v rsov ), rst t erminal changes open to low after the propagation delay (t prst ). the glitch within t prst does not affect the power good monitor output. ld2 pgl2 enabling ld2 is followed by rising of the ld2 output voltage (v outl2 ). once v outl2 reaches within the power good range (v pguv + v pguvhys < v outl2 < v pgov C v pgovhys ) , the power good monitor output (pgl2 terminal) changes its state from low to open through the power - on - reset time (t rpg ). when v outl2 is out of the power good range (v outl2 v pguv or v outl2 v pgov ), pgl2 terminal changes open to low after the propagation delay (t ppg ). the glitch within t ppg does not affect the power good monitor output. figure 10 - 9 power - good monit or output timing chart (pg1, pg2, pg3, pg4, pgl2) figure 10 - 10 power - good monitor output timing chart (rst) time v pg1 ,v pg2 , v pg3 ,v pg4 , v pgl2 t rpg < t ppg t ppg v en1 ,v en2 , v en3 ,v en4 , v enl2 v out1 ,v out2 , v out3 ,v out4 , v outl2 < t ppg not reset t rpg v pgovhys v pguvhys v pgov v pguv t ppg t rpg time v rst t rd < t prst t prst v enl1 v outl1 < t prst not reset t rd v rsovhys v rsuvhys v rsov v rsuv t prst t rd
document number: 002 - 03341 rev.*c page 25 of 38 s6bp401a 10.9 watchdog timer s6bp401a employs a digital windowed watchdog timer. the digital windowed watchdog timer starts monitoring trigger signal, when the ld1 output voltage (v outl1 ) reaches the power good level after enabling ld1. figure 10 - 11 s hows the state diagram of the digital watchdog timer. there are six states in the diagram. in the normal operation, the state is expected to move back and forth between cw and ow, at first, as described in the section 10.8 , enabling ld1 brings reset state, and the reset state is kept for the reset time (t rd ) outputting low from rst terminal. in the second, after t rd in the reset state, the state will transition to ignore window (iw), and let rst terminal be open. the iw state will be elapsed in the ignore window time (t iw .) in the third, after elapsing, the state will transition will transition to long open window (low) state, and let rst te rminal be open. in this state, a trigger signal is expected to be input: if an input trigger arrives, the state will immediately tran sition to the closed window (cw) state. without an input trigger in the long open window time (t low ,) the state will be elapsed and will transition to reset state. in the cw state, a trigger signal is expected not to be input: if an input trigger arrives, the state will immediately tran sition to the reset state. without an input trigger in the closed window time ( t cw ,) the state will be elapsed and will transition to open window (ow) state. in the ow state, a trigger signal is expected not to be input: if an input trigger arrives, the state will immediately tran sition to the reset state. without an input tri gger in the open window time (t ow ,) the state will be elapsed and will transition to closed window (cw) state. in any states above, a power failure of ld1 will cause a transition to off state, and output low from rst terminal until ld1 goes well. figure 10 - 11 watchdog timer state diagram off rst=low reset rst=low iw rst=open long ow rst=open ow rst=open cw rst=open ld1 power fail ld1 power fail ld1 power fail trigger ld1 power fail no trigger (t ow timeout) trigger no trigger (t cw timeout) ld1 power good t rd timeout t iw timeout trigger no trigger (t low timeout) ld1 power fail
document number: 002 - 03341 rev.*c page 26 of 38 s6bp401a figure 10 - 12 window watchdog timing chart (wdi) figure 10 - 13 window watchdog timing chart (ld1) time v wdi v outl1 ignore v rsuv v rst iw long ow cw ow cw ow iw reset long ow cw reset iw long ow reset iw reset off t iw t rd document number: 002 - 03341 rev.*c page 27 of 38 s6bp401a figure 10 - 14 de - glitch of window watchdog trigger pulse window time closed window open window closed window t ow t cw t cw t sam h h l l h h l l h h l l h h l l : sampling point valid valid not valid not valid watchdog trigger pulse l h l l h h l h not valid not valid
document number: 002 - 03341 rev.*c page 28 of 38 s6bp401a 10.10 internal linear regulator output (vreg) s6bp401a equips a 1.8v linear regulator as the power source for its internal circuit. a low esr 1.0f ceramic capacitor should be connected from vreg pin to gnd. vreg is not designed to supply to external load. unless the vreg terminal voltage is in the range between the over voltage lockout level v vregovr and the under voltage lockout level v vreguvf , s6bp401a considers it abnormal and halts all dc/dc converters, ldos and windowed watchdog timer. when the vreg terminal voltage returns to the power good voltage range (v vreguvr v vreg v vregovf ), s6bp401a returns t he dc/dc converters, ldos and window watchdog timer to the normal mode . soft - start circuits of each regulator gradually generates supply voltage as described in the section 10.6 . figure 10 - 15 v reg ovlo/uvlo timing chart v vreg time v vreguvf v vregovr v vregovf v vreguvr v en1 ,v en2 , v en3 ,v en4 , v enl1 ,v enl2 v out1 soft - start soft - start soft - start v out2 soft - start soft - start soft - start v out3 soft - start soft - start soft - start v out4 soft - start soft - start soft - start v outl1 soft - start soft - start soft - start v outl2 soft - start soft - start soft - start initialization initialization initialization
document number: 002 - 03341 rev.*c page 29 of 38 s6bp401a 11. application circuit example figure 11 - 1 application circuit example p v c c 1 2 9 l x 1 2 8 p g n d 1 2 7 p v c c 2 a 2 1 p v c c 2 b 2 2 l x 2 a 2 3 l x 2 b 2 4 p g n d 2 a 2 5 p g n d 2 b 2 6 p v c c 3 8 l x 3 7 p g n d 3 6 p v c c 4 3 l x 4 4 p g n d 4 5 p v c c l 1 3 6 l d o 1 3 5 p v c c l 2 3 7 l d o 2 3 8 p g 1 3 3 p g 2 3 1 p g 3 1 0 p g 4 1 p g l 2 4 0 r s t 1 3 w d i 1 2 f b 1 3 0 f b 2 2 0 f b 3 9 f b 4 2 e n 1 1 9 e n 2 1 8 e n 3 1 7 e n 4 1 6 e n l 1 1 5 e n l 2 1 4 v c c 3 4 v r e g 3 2 s y n c 1 1 g n d 3 9 e p 4 1 c p 1 4 2 c p 2 4 3 c p 3 4 4 c p 4 4 5 s 6 b p 4 0 1 a m 1 v i n v i n v i n v i n v i n v i n v o u t 1 v o u t 2 v o u t 3 v o u t 4 v o u t l 1 v o u t l 2 v o u t 1 v o u t 2 v o u t 3 v o u t 4 r s t w d i v o u t l 1 o r v i n v o u t 4 o r v i n r 1 0 r 9 r 8 r 7 r 6 r 5 c 3 1 c 1 l 1 c 1 5 l 3 c 2 1 l 4 c 7 l 2 c 2 7 c 2 8 c 3 0 c 3 3 c 3 4 c 2 c 3 c 1 6 c 1 7 c 2 2 c 2 3 c 8 c 9 c 1 0 p g 1 p g 2 p g 3 p g 4 p g l 2 e n 1 e n 2 e n 3 e n 4 e n l 1 e n l 2 v o u t 1 v o u t 2 v o u t 3 v o u t 4 v o u t l 1 v o u t l 2 v i n 5 v g n d
document number: 002 - 03341 rev.*c page 30 of 38 s6bp401a table 11 - 1 parts list symbol parts part number specifications vendor c1 ceramic capacitor cga5l1x7r1c106k160ac 10 f tdk c2 ceramic capacitor cga6p1x7r1c226m250ac 22 f tdk c3 ceramic capacitor cga6p1x7r1c226m250ac 22 f tdk c7 ceramic capacitor cga5l1x7r1c106k160ac 10 f tdk c8 ceramic capacitor cga6p1x7r1c226m250ac 22 f tdk c9 ceramic capacitor cga6p1x7r1c226m250ac 22 f tdk c10 ceramic capacitor cga6p1x7r1c226m250ac 22 f tdk c15 ceramic capacitor cga5l1x7r1c106k160ac 10 f tdk c16 ceramic capacitor cga6p1x7r1c226m250ac 22 f tdk c17 ceramic capacitor cga6p1x7r1c226m250ac 22 f tdk c21 ceramic capacitor cga5l1x7r1c106k160ac 10 f tdk c22 ceramic capacitor cga6p1x7r1c226m250ac 22 f tdk c23 ceramic capacitor cga6p1x7r1c226m250ac 22 f tdk c27 ceramic capacitor cga3e1x7r1c105m080ac 1 f tdk c28 ceramic capacitor cga3e1x7r1c105m080ac 1 f tdk c30 ceramic capacitor cga3e1x7r1c105m080ac 1 f tdk c31 ceramic capacitor cga5l1x7r1c106k160ac 10 f tdk c33 ceramic capacitor cga3e1x7r1c105m080ac 1 f tdk c34 ceramic capacitor cga3e1x7r1c105m080ac 1 f tdk l1 inductor clf6045t - 1r5n - d 1.5 h tdk l2 inductor clf6045t - 1r5n - d 1.5 h tdk l3 inductor clf6045t - 1r5n - d 1.5 h tdk l4 inductor clf6045t - 1r5n - d 1.5 h tdk r5 resistor rg1608p - 473 - b 47 k ssm r6 resistor rg1608p - 473 - b 47 k ssm r7 resistor rg1608p - 473 - b 47 k ssm r8 resistor rg1608p - 473 - b 47 k ssm r9 resistor rg1608p - 473 - b 47 k ssm r10 resistor rg1608p - 473 - b 47 k ssm tdk : tdk corporation ssm : susumu co., ltd.
document number: 002 - 03341 rev.*c page 31 of 38 s6bp401a 12. reference data the followings are the reference data measured under the conditions shown in 11 . application circuit example . figure 12 - 1 dc/dc converter d d 1 e f f i c i e n c y [ % ] i o u t 1 [ a ] 0 1 0 0 4 1 0 s 6 b p 4 0 1 a g r a p h 0 0 2 2 0 4 0 5 0 6 0 7 0 d d 1 e f f i c i e n c y v s i o u t 1 v v c c = v p v c c 1 = 5 . 0 v 3 0 8 0 9 0 1 0 . 1 0 . 0 1 0 . 0 0 1 p r e s e t o u t p u t v o l t a g e = 1 . 2 5 0 v t a = + 2 5 o c t a = o c t a = + 1 2 5 o c v o u t 1 [ v ] i o u t 1 [ a ] 1 . 2 0 0 2 . 0 s 6 b p 4 0 1 a g r a p h 0 0 3 1 . 2 3 0 d d 1 l o a d r e g u l a t i o n v v c c = v p v c c 1 = 5 . 0 v 1 . 2 2 0 1 . 2 1 0 1 . 2 4 0 1 . 2 5 0 1 . 2 6 0 1 . 2 7 0 1 . 2 8 0 1 . 4 1 . 0 0 . 8 0 . 4 0 1 . 8 p r e s e t o u t p u t v o l t a g e = 1 . 2 5 0 v 1 . 6 1 . 2 0 . 2 0 . 6 t a = + 1 2 5 o c t a = + 2 5 o c t a = o c v v c c = v p v c c 1 = 5 . 0 v , t a = + 2 5 o c , p r e s e t o u t p u t v o l t a g e = 1 . 2 5 0 v 1 0 s / d i v s 6 b p 4 0 1 a g r a p h 0 0 8 i o u t 1 2 a / d i v d d 1 l o a d t r a n s i e n t r e s p o n s e v p g 1 1 0 v / d i v v o u t 1 2 0 m v / d i v o f f s e t 1 . 2 5 0 v 1 0 s / d i v s 6 b p 4 0 1 a g r a p h 0 0 8 1 i o u t 1 2 a / d i v d d 1 l o a d t r a n s i e n t r e s p o n s e v p g 1 1 0 v / d i v v o u t 1 2 0 m v / d i v o f f s e t 1 . 2 5 0 v v v c c = v p v c c 1 = 5 . 0 v , t a = + 2 5 o c , p r e s e t o u t p u t v o l t a g e = 1 . 2 5 0 v t a = + 2 5 o c t a = o c d d 2 e f f i c i e n c y [ % ] i o u t 2 [ a ] 0 1 0 0 4 1 0 s 6 b p 4 0 1 a g r a p h 0 1 1 2 0 4 0 5 0 6 0 7 0 d d 2 e f f i c i e n c y v s i o u t 2 v v c c = v p v c c 2 = 5 . 0 v 3 0 8 0 9 0 1 0 . 1 0 . 0 1 0 . 0 0 1 p r e s e t o u t p u t v o l t a g e = 1 . 1 2 5 v t a = + 1 2 5 o c v o u t 1 [ v ] i o u t 2 [ a ] 1 . 0 8 0 3 . 0 s 6 b p 4 0 1 a g r a p h 0 1 2 1 . 1 1 0 d d 2 l o a d r e g u l a t i o n v v c c = v p v c c 2 = 5 . 0 v 1 . 1 0 0 1 . 0 9 0 1 . 1 2 0 1 . 1 3 0 1 . 1 4 0 1 . 1 5 0 1 . 1 6 0 2 . 0 1 . 5 1 . 0 0 . 5 0 2 . 5 p r e s e t o u t p u t v o l t a g e = 1 . 1 2 5 v t a = + 1 2 5 o c t a = + 2 5 o c t a = o c v v c c = v p v c c 2 = 5 . 0 v , t a = + 2 5 o c , p r e s e t o u t p u t v o l t a g e = 1 . 1 2 5 v 1 0 s / d i v s 6 b p 4 0 1 a g r a p h 0 1 7 i o u t 2 2 a / d i v d d 2 l o a d t r a n s i e n t r e s p o n s e v p g 2 1 0 v / d i v v o u t 2 2 0 m v / d i v o f f s e t 1 . 1 2 5 v 1 0 s / d i v s 6 b p 4 0 1 a g r a p h 0 1 7 1 i o u t 2 2 a / d i v d d 2 l o a d t r a n s i e n t r e s p o n s e v p g 2 1 0 v / d i v v o u t 2 2 0 m v / d i v o f f s e t 1 . 1 2 5 v v v c c = v p v c c 2 = 5 . 0 v , t a = + 2 5 o c , p r e s e t o u t p u t v o l t a g e = 1 . 1 2 5 v t a = + 2 5 o c t a = o c d d 3 e f f i c i e n c y [ % ] i o u t 3 [ a ] 0 1 0 0 4 1 0 s 6 b p 4 0 1 a g r a p h 0 2 0 2 0 4 0 5 0 6 0 7 0 d d 3 e f f i c i e n c y v s i o u t 3 v v c c = v p v c c 3 = 5 . 0 v 3 0 8 0 9 0 1 0 . 1 0 . 0 1 0 . 0 0 1 p r e s e t o u t p u t v o l t a g e = 2 . 5 5 0 v t a = + 1 2 5 o c
document number: 002 - 03341 rev.*c page 32 of 38 s6bp401a v o u t 3 [ v ] i o u t 3 [ a ] 2 . 5 0 0 2 . 0 s 6 b p 4 0 1 a g r a p h 0 2 1 2 . 5 3 0 d d 3 l o a d r e g u l a t i o n v v c c = v p v c c 3 = 5 . 0 v 2 . 5 2 0 2 . 5 1 0 2 . 5 4 0 2 . 5 5 0 2 . 5 6 0 2 . 5 7 0 2 . 5 8 0 1 . 2 1 . 0 0 . 8 0 . 2 0 1 . 6 p r e s e t o u t p u t v o l t a g e = 2 . 5 5 0 v 1 . 4 1 . 8 0 . 4 0 . 6 t a = + 1 2 5 o c t a = + 2 5 o c t a = o c v v c c = v p v c c 3 = 5 . 0 v , t a = + 2 5 o c , p r e s e t o u t p u t v o l t a g e = 2 . 5 5 0 v 1 0 s / d i v s 6 b p 4 0 1 a g r a p h 0 2 6 i o u t 3 2 a / d i v d d 3 l o a d t r a n s i e n t r e s p o n s e v p g 3 1 0 v / d i v v o u t 3 5 0 m v / d i v o f f s e t 2 . 5 5 0 v 1 0 s / d i v s 6 b p 4 0 1 a g r a p h 0 2 6 1 i o u t 3 2 a / d i v d d 3 l o a d t r a n s i e n t r e s p o n s e v p g 3 1 0 v / d i v v o u t 3 5 0 m v / d i v o f f s e t 2 . 5 5 0 v v v c c = v p v c c 3 = 5 . 0 v , t a = + 2 5 o c , p r e s e t o u t p u t v o l t a g e = 2 . 5 5 0 v d d 4 e f f i c i e n c y [ % ] i o u t 4 [ a ] 0 1 0 0 4 1 0 s 6 b p 4 0 1 a g r a p h 0 2 9 2 0 4 0 5 0 6 0 7 0 d d 4 e f f i c i e n c y v s i o u t 4 v v c c = v p v c c 4 = 5 . 0 v 3 0 8 0 9 0 1 0 . 1 0 . 0 1 0 . 0 0 1 p r e s e t o u t p u t v o l t a g e = 3 . 3 7 5 v t a = + 1 2 5 o c t a = + 2 5 o c t a = o c v o u t 4 [ v ] i o u t 4 [ a ] 3 . 3 2 0 1 . 0 s 6 b p 4 0 1 a g r a p h 0 3 0 3 . 3 5 0 d d 4 l o a d r e g u l a t i o n v v c c = v p v c c 4 = 5 . 0 v 3 . 3 4 0 3 . 3 3 0 3 . 3 6 0 3 . 3 7 0 3 . 3 8 0 3 . 3 9 0 3 . 4 0 0 0 . 6 0 . 5 0 . 3 0 . 1 0 t a = + 1 2 5 o c t a = + 2 5 o c t a = o c 0 . 7 0 . 8 0 . 9 0 . 2 0 . 4 p r e s e t o u t p u t v o l t a g e = 3 . 3 7 5 v v v c c = v p v c c 4 = 5 . 0 v , t a = + 2 5 o c , p r e s e t o u t p u t v o l t a g e = 3 . 3 7 5 v 1 0 s / d i v s 6 b p 4 0 1 a g r a p h 0 3 5 i o u t 4 1 a / d i v d d 4 l o a d t r a n s i e n t r e s p o n s e v p g 4 1 0 v / d i v v o u t 4 5 0 m v / d i v o f f s e t 3 . 3 7 5 v 1 0 s / d i v s 6 b p 4 0 1 a g r a p h 0 3 5 1 i o u t 4 1 a / d i v d d 4 l o a d t r a n s i e n t r e s p o n s e v p g 4 1 0 v / d i v v o u t 4 5 0 m v / d i v o f f s e t 3 . 3 7 5 v v v c c = v p v c c 4 = 5 . 0 v , t a = + 2 5 o c , p r e s e t o u t p u t v o l t a g e = 3 . 3 7 5 v f o s c [ m h z ] 2 . 0 0 s 6 b p 4 0 1 a g r a p h 0 5 3 1 f o s c v s v v c c 2 . 0 4 2 . 0 8 2 . 1 6 v v c c [ v ] 5 . 5 4 . 5 4 . 0 3 . 5 5 . 0 2 . 0 6 2 . 0 2 2 . 1 0 2 . 1 2 2 . 1 4 t a = o c t a = + 2 5 o c t a = + 1 2 5 o c
document number: 002 - 03341 rev.*c page 33 of 38 s6bp401a figure 12 - 2 ldo regulator v o u t l 1 [ v ] i o u t l 1 [ a ] 3 . 3 0 0 0 . 2 s 6 b p 4 0 1 a g r a p h 0 3 8 3 . 3 3 0 l d 1 l o a d r e g u l a t i o n v v c c = v p v c c l 1 = 5 . 0 v 3 . 3 2 0 3 . 3 1 0 3 . 3 4 0 3 . 3 5 0 3 . 3 6 0 3 . 3 7 0 3 . 3 8 0 0 . 1 0 . 0 5 0 0 . 1 5 t a = + 2 5 o c t a = o c t a = + 1 2 5 o c p r e s e t o u t p u t v o l t a g e = 3 . 3 2 5 v v v c c = v p v c c l 1 = 5 . 0 v , t a = + 2 5 o c , p r e s e t o u t p u t v o l t a g e = 3 . 3 2 5 v 1 0 s / d i v s 6 b p 4 0 1 a g r a p h 0 4 3 i o u t l 1 0 . 2 a / d i v l d 1 l o a d t r a n s i e n t r e s p o n s e v r s t 1 0 v / d i v v o u t l 1 5 0 m v / d i v o f f s e t 3 . 3 2 5 4 0 0 s / d i v s 6 b p 4 0 1 a g r a p h 0 4 3 1 i o u t l 1 0 . 2 a / d i v l d 1 l o a d t r a n s i e n t r e s p o n s e v r s t 1 0 v / d i v v o u t l 1 5 0 m v / d i v o f f s e t 3 . 3 2 5 v v v c c = v p v c c l 1 = 5 . 0 v , t a = + 2 5 o c , p r e s e t o u t p u t v o l t a g e = 3 . 3 2 5 v v o u t l 2 [ v ] i o u t l 2 [ a ] 2 . 7 7 0 0 . 5 s 6 b p 4 0 1 a g r a p h 0 4 5 2 . 8 0 0 l d 2 l o a d r e g u l a t i o n v v c c = v p v c c l 2 = 5 . 0 v 2 . 7 9 0 2 . 7 8 0 2 . 8 1 0 2 . 8 2 0 2 . 8 3 0 2 . 8 4 0 2 . 8 5 0 0 . 3 0 . 1 0 0 . 4 t a = + 2 5 o c t a = o c t a = + 1 2 5 o c p r e s e t o u t p u t v o l t a g e = 2 . 8 0 0 v 0 . 2 v v c c = v p v c c l 2 = 5 . 0 v , t a = + 2 5 o c , p r e s e t o u t p u t v o l t a g e = 2 . 8 0 0 v 1 0 s / d i v s 6 b p 4 0 1 a g r a p h 0 5 0 i o u t l 2 0 . 5 a / d i v l d 2 l o a d t r a n s i e n t r e s p o n s e v p g l 2 1 0 v / d i v v o u t l 2 2 0 m v / d i v o f f s e t 2 . 8 0 0 v 4 0 0 s / d i v s 6 b p 4 0 1 a g r a p h 0 5 0 1 i o u t l 2 0 . 5 a / d i v l d 2 l o a d t r a n s i e n t r e s p o n s e v p g l 2 1 0 v / d i v v o u t l 2 2 0 m v / d i v o f f s e t 2 . 8 0 0 v v v c c = v p v c c l 2 = 5 . 0 v , t a = + 2 5 o c , p r e s e t o u t p u t v o l t a g e = 2 . 8 0 0 v
document number: 002 - 03341 rev.*c page 34 of 38 s6bp401a 13. ordering information table 13 - 1 ordering information part n umber (mpn) (*1) output voltage [v] package dd1 dd2 dd3 dd4 ld1 ld2 s6bp401ab1sn1b000 1.250 1.250 1.250 3.375 3.325 1.850 p lastic , qfn ( 0. 50 mm p itch) , 40 - pin ( vn d 0 40 ) S6BP401AE0SN1B000 1.200 1.000 1.500 3.300 3.300 1.800 s6bp401ae1sn1b000 1.200 1.100 1.500 3.300 3.300 1.800 s6bp401aj0sn1b000 1.250 1.250 1.850 3.375 3.300 2.800 s6bp401aj1sn1b000 1.200 1.000 1.800 3.300 3.300 2.800 s6bp401aj2sn1b000 1.200 1.100 1.800 3.300 3.300 2.800 s6bp401al0sn1b000 1.200 1.000 2.500 3.300 3.300 1.800 s6bp401al1sn1b000 1.200 1.100 2.500 3.300 3.300 1.800 s6bp401al 2 sn1b000 1.2 5 0 1.1 25 2.5 5 0 3.3 75 3.3 25 1.8 5 0 s6bp401am2sn1b000 1.250 1.125 2.550 3.375 3.325 2.800 s6bp401aw 0 sn1b000 1.500 1.100 1.800 3.300 3.300 2.800 s6bp401ay0sn1b000 1.500 1.000 2.500 3.300 3.300 1.800 s6bp401ay1sn1b000 1.500 1.100 2.500 3.300 3.300 1.800 s6bp401ay2sn1b000 1.500 1. 2 00 2.500 3.300 3.300 1.800 mpn: marketing part number *1: please contact our sales division for the output voltage co mb ination not mentioned in this table. part numbering conventions these ic s follow the part numbering convention described in the following table. each single - character is alphanumeric (0, 1, 2, , 9, a, b, , z) unless stated otherwise. the part numbers are defined as follows. s 6 b p 4 0 1 a x x s n 1 b 0 0 0 f i x e d o n 0 0 0 p a c k i n g : b = 1 3 i n c h t a p e a n d r e e l p a c k a g e : n 1 = q f n , p d - p p f / l o w - h a l o g e n r e l i a b i l i t y g r a d e : s = 1 0 p p m p r e s e t c o n d i t i o n r e v i s i o n : a = 1 s t r e v i s i o n p r o d u c t i d : 0 1 t o p o l o g y : 4 = s w i t c h - m o d e p o w e r s u p p l y p r o d u c t t y p e : p = p o w e r m a n a g e m e n t i c p r o d u c t c l a s s : 6 b = a u t o m o t i v e a n a l o g c o m p a n y i d : s = c y p r e s s
document number: 002 - 03341 rev.*c page 35 of 38 s6bp401a 14. package dimensions
document number: 002 - 03341 rev.*c page 36 of 38 s6bp401a 15. m ajor c hanges spansion publication number: s6bp401a_ds405 - 0002 4 page section change results revision 0 . 1 ( february 19, 2015 ) - - initial release note: please see document history about later revised information. document history document title: s6bp401a power management ic for automotive adas platform document number: 002 - 03341 revision ecn orig. of change submission date description of change ** 4922113 ymae 0 9 / 16 /2015 new spec. updated ordering information *a 5085035 hixt 01 / 1 4 /201 6 upd ated 3 . pin functions updated 6 . absolute maximum ratings updated 7 . recommended operating conditions added development support added 12 . reference data updated 13 . ordering information * b 5160391 hixt 0 3 / 04 /201 6 added aec - q100 compliant (grade - 1) in features added the following values in 8 . electrical characteristics supply c urrent i vccs : max value uvlo: under v oltage l ockout (vcc) v uvhys : min and max values enable i nputs (en1, en2, en3, en4, enl1, enl2) i ih en : min and max values synchronization i nput (sync) i ih sync : min and max values power good monitor (pg1, pg2, pg3, pg4, pgl2, rst) v pgovhys : min and max values v pguvhys : min and max values watchdog timer (wdi) t wd : min and max values i ih wdi : min and max values dd1: buck dc/dc c onverter r fb1 : min and max values r onhs1 : max values r onls1 : max values i leak1 : max value v ovphys1 : min and max values r dis1 : min and max values t coess1 : min and max values dd2: buck dc/dc c onverter r fb2 : min and max values r onhs2 : max values r onls2 : max values
document number: 002 - 03341 rev.*c page 37 of 38 s6bp401a revision ecn orig. of change submission date description of change * b 5160391 hixt 0 3 / 04 /201 6 i leak2 : max value v ovphys2 : min and max values r dis2 : min and max values t coess2 : min and max values dd3: buck dc/dc c onverter r fb3 : min and max values r onhs3 : max values r onls3 : max values i leak3 : max value v ovphys3 : min and max values r dis3 : min and max values t coess3 : min and max values dd4: buck dc/dc c onverter r fb4 : min and max values r onhs4 : max values r onls4 : max values i leak4 : max value v ovphys4 : min and max values r dis4 : min and max values t coess4 : min and max values ld1: ldo r egulator i leakl1 : max value r disl1 : min and max values t coessl1 : min and max values ld2: ldo r egulator i leakl 2 : max value r disl 2 : min and max values t coessl 2 : min and max values updated the following values in 8 . electrical characteristics dd1: buck dc/dc c onverter r onhs1 : typ value r onls1 : typ value dd2 : buck dc/dc c onverter r onhs2 : typ value r onls2 : typ value dd3 : buck dc/dc c onverter r onhs3 : typ value r onls3 : typ value dd4 : buck dc/dc c onverter r onhs4 : typ value r onls4 : typ value delete the following values in 8 . electrical characteristics updated figure 10 - 1 and figure 10 - 2 updated 10.5 under voltage lockout (uvlo) added a part number, s6bp401al2sn1b000 , in table 13 - 1 . c orrected an error in table 13 - 1 . from s6bp401aw1sn1b000 to s6bp401aw0sn1b000 * c 5396389 hixt 08 / 0 9 /201 6 deleted development support and ad ded more information added s6bp401ay2sn1b000 to table 13 - 1 ordering information
document number: 002 - 03341 rev.*c august 9, 2016 page 38 of 38 s6bp401a sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution centers, manufacturers representatives, and distributors. to find the office closest to you, visit us at cypress locations . products arm ? cortex ? microcontrollers cypress.com/a rm automotive cypress.com/automotive clocks & buffers cypress.com/clocks interface cypress.com/interface lighting & power control cypress.com/powerpsoc memory cypress.com/memory psoc cypress.com/psoc touch sensing cypress.com/touch usb controlle rs cypress.com/ usb wireless/rf cypress.com/wireless psoc? solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training | co mp onents technical support cypress.com/support arm and cortex are the registered trademarks of arm limited in the eu and other countries. ? cypress semiconductor corporation, 2015 - 2016 . this document is the property of cypress semiconductor corporation and its subsidiaries, including spansion llc (cypress) . this document, including any software or firmware included or referenced in this document (software), is owned by cypress under the intellectual property laws and t reaties of the united states and other countries worldwide. cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. if the software is not accompanied by a license agreement and you do not otherwise have a written agreeme nt with cypress governing the use of the software, then cypress hereby grants you a personal, non - exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the software (a) for s oftware provided in source code f orm, to modify and reproduce the software solely for use with cypress hardware products, only internally within your organiza tion, and (b) to distribute the software in binary code form externally to end users (either directly or indirectly through reselle rs and distributors), solely for use on cypress hardware product units, and (2) under those claims of cypresss patents that are infringed by the software (as provided by cypress, unmodified) to make, use, distribute, and import the software solely for u se with cypress hardware products. any other use, reproduction, modification, translation, or compilation of the software is prohibited. to the extent permitted by applicable law, cypress makes no warranty of any kind, express or implied, with regard to thi s document or any software or accompanying hardware, including, but not limited to, the implied warranties of merchantability and fitness for a particul ar purpose. to the extent permitted by applicable law, cypress reserves the right to make changes to thi s document without further notice. cypress does not assume any liability arising out of the application or use of any product or circuit described in this document. any information provided in this document, including any sample design inform ation or prog ramming code, is provided only for reference purposes. it is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the ope ration of weapons, weapons systems, nuclear installations, life - support devices or systems, other medical devices or systems (incl uding resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses whe re the failure of the device or system could cause personal injury, death, or property damage (unintended uses). a critical comp onent is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. cypress i s not liable, in whole or in part, and you shall and hereby d o release cypress from any claim, damage, or other liability arising from or related to all unintended uses of cypress products. you shall ind emnify and hold cypress harmless from and against all claims, costs, damages, and other liabilities, including cl aims for personal injury or death, arising from or related to any unintended uses of cypress products. cypress, the cypress logo, spansion, the spansion logo, and combinations thereof, psoc, capsense, ez - usb, f - ram, and traveo are trademarks or registered trademarks of cypress in the united states and other countries. for a more complete list of cypress trademarks, visit cypress.com. other names and brand s may be claimed as property of their respective owners.

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